How many bits are needed for the program counter

Term what are the technical advantages of having a family architecture E. Definition different series have different strengths depending on what type of machine you're developing one might be more beneficial than the other. Term what is the objective of this course? Definition to learn the functions and architecture of different parts of a computer memory such as registers and the cpu. Term explain the functioning of synchronis and asynchronis data transfer. Definition synchronis data transfer functions sequentially by transfering data one after the other at clock pulses asynchronis data transfers does not function sequentially, it transfers data randomly between clock pulses.

Term what is the differences among sequencial, direct, and random accesses? Definition sequencial access is data thats accessed one after the other direct - is a particular portion of data is accessed directly. Term A set associative cache has a block size of two bi words and a set size of 4.

The chache can accommodate a total of 4K bit words from the main memory. Design the cache structure, by a. Definition hmk4 4 just change tag set word to 12,10,2 respectivly. Definition 0. Term In the Intel architecture, the addresses are staggered into two separate units e. What might be the purpose of this technique?

Definition Double Words can be accessed in parallel in the same time required to access a Word. Term Go back to HW 1 Question 1 b. Discuss the impact on the system speed if the microprocessor has: i a bit local address bus and a bit local data bus, or ii a bit local address bus and a bit local data bus. Definition b1: If the local address bus is 32 bits, the whole address can be transferred at once and decoded in memory.

However, since the data bus is only 16 bits, it will require 2 cycles to fetch a bit instruction operand. Thus a more complex memory interface control is needed to latch the first part of the address and then the second part since the microprocessor will end in 2 steps.

Term Go back to HW 1 Question 1 c. How many bits are needed for the program counter and the instruction register? Definition c: The PC must be at least 24 bits. Typically, a bit microprocessor will have a bit external address bus and a bit program counter, unless on-chip segment registers are used that may work with a smaller program counter.

If the IR is to contain the whole instruction, it will have to be 32 bits long. If it will contain the op code called the op code register then it will have to be 8 bits long. Term Go back to HW 1 Question 2 a. Term Go back to HW 1 Question 2 b. Term Go back to HW 1 Question 2 c. Definition c: Separate input and output instructions are needed whose execution will generate separate input and output signals different from memory signals generated by executing memory-type instructions.

What is the maximum directly addressable memory capacity in bytes. Computer Architecture. Consider a hypothetical bit microprocessor having bit instructions: Solutions Problem Set: Consider a hypothetical bit microprocessor having bit instructions composed of two fields: the first byte contains the opcode and the remainder the immediate operand or an operand address.

What is the maximum directly addressable memory capacity in bytes? Discuss the impact on the system speed if the microprocessor bus has 1. How many bits are needed for the program counter and the instruction register? Solution: a. The reason why you need both is because if you only had a program counter and used it for both purposes you would get the following troublesome system:. Therefore, we need another register to hold the actual instruction fetched from memory. Once we fetch that memory, we increase PC so that we know where to fetch the next instruction.

For example, for a bit processor, the word size is bits. Therefore, the registers on the CPU would be 32 bits. Instruction registers are no different in dimensions. The difference is in the behavior and interpretation. Instructions are encoded in various forms, however, they still occupy a bit register.

For example, the Nios II processor from Altera contains 3 different instruction types, each encoded differently. You can learn more about the Nios II processor's structure from the link above as well. As you stated, the Program Counter PC holds the address of the next instruction to execute, and the Instruction Register IR stores the actual instruction to be executed but not its address.

Related to the lenght of these registers, current machines have bit PCs. The length of the IR from a logical point of view depends on the architecture:. As these machines are able to fetch, decode and execute several instructions every cycle, the physical implementation of the IR is not easy to describe in a few lines. Supporting PAE to get the extra 4 bits of address space was a royal pain.

And yes, any process can only address a total maximum of 4GB on 32bit Windows. However there is a use case that does not involve a large number of small processes: Windows, both workstation and server, will use otherwise unused chip memory for disk cache. Workhorse was, among other things, a fairly large server system, so being able to cache a lot of data was definitely beneficial. For instance - An 8kB memory needs 13 bits to address it bytewise.

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